1. Field of the Invention
Generally, the present disclosure relates to the field of integrated circuits, and, more particularly, to the manufacture of field effect transistors on the basis of nitrogen-containing dielectric layers, such as stressed contact etch stop layers used for generating strain in channel regions of the transistors.
2. Description of the Related Art
Integrated circuits are typically comprised of a large number of circuit elements located on a given chip area according to a specified circuit layout, wherein, in complex circuits, the field effect transistor represents one predominant circuit element. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry based on field effect transistors, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches, due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region.
The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed above the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One problem in this respect is the development of enhanced photolithography and etch strategies to reliably and reproducibly create circuit elements of critical dimensions, such as the gate electrode of the transistors, for a new device generation. Moreover, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions to provide low sheet and contact resistivity in combination with a desired channel controllability.
A further issue associated with reduced gate lengths is the occurrence of so-called short channel effects, which may result in a reduced controllability of the channel conductivity. Short channel effects may be countered by appropriately scaling the capacitive coupling of the gate electrode to the channel region, for instance by reducing the thickness of the gate insulation layer, providing enhanced dopant profiles in the channel region and in adjacent drain and source areas and the like. However, some of these design measures, such as increasing the dopant concentration in the channel region or the provision of high-k dielectrics in the gate insulation layer, may be accompanied by a reduction of the channel conductivity, thereby partially offsetting the advantages obtained by the reduction of critical dimensions.
In view of this situation, it has been proposed to enhance device performance of the transistor elements not only by reducing the transistor dimensions but also by increasing the charge carrier mobility in the channel region for a given channel length, thereby increasing the drive current capability and thus transistor performance. In principle, at least two mechanisms may be used, in combination or separately, to increase the mobility of the charge carriers in the channel region. First, the dopant concentration within the channel region may be reduced, thereby reducing scattering events for the charge carriers and thus increasing the conductivity. However, reducing the dopant concentration in the channel region significantly affects the threshold voltage of the transistor device, while the reduced channel length may even require enhanced dopant concentrations in order to control short channel effects, thereby making a reduction of the dopant concentration a less attractive approach unless other mechanisms are developed to adjust a desired threshold voltage. Second, the lattice structure in the channel region may be modified, for instance by creating tensile or compressive strain therein, which results in a modified mobility for electrons and holes, respectively. For example, creating tensile strain in the channel region of a silicon layer having a standard crystallographic configuration may increase the mobility of electrons, which, in turn, may directly translate into a corresponding increase of the conductivity of N-type transistors. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors.
One promising approach in this respect is a technique that enables the creation of desired stress conditions within the channel region of different transistor elements by adjusting the stress characteristics of a contact etch stop layer that is formed above the basic transistor structure in order to form contact openings to the gate and drain and source terminals in an interlayer dielectric material. The effective control of mechanical stress in the channel region, i.e., effective stress engineering, may be accomplished by individually adjusting the internal stress in the contact etch stop layer of the respective transistor in order to position a contact etch contact layer having an internal compressive stress above a P-channel transistor while positioning a contact etch stop layer having an internal tensile strain above an N-channel transistor, thereby creating compressive and tensile strain, respectively, in the respective channel regions.
Typically, the contact etch stop layer is formed by plasma enhanced chemical vapor deposition processes (PECVD) above the transistor, i.e., above the gate structure and the drain and source regions, wherein, for instance, silicon nitride may be used, due to its high etch selectivity with respect to silicon dioxide, which is a well-established interlayer dielectric material. Furthermore, PECVD silicon nitride may be deposited with a high intrinsic stress, for example, up to 2 Giga Pascal (GPa) or significantly higher for compressive stress and up to 1 GPa and significantly higher for tensile stress, wherein the type and the magnitude of the intrinsic stress may be efficiently adjusted by selecting appropriate deposition parameters. For example, ion bombardment, deposition pressure, substrate temperature, gas components and the like represent respective parameters that may be used for obtaining the desired intrinsic stress.
In a typical process sequence, a contact etch stop layer having compressive stress is formed above the transistors after completing the formation of respective metal silicide regions. In order to protect the silicide regions during the further patterning process, a stop layer formed of silicon dioxide may be provided prior to depositing the compressive etch stop layer. Then, a thin etch indicator layer comprised of silicon dioxide is formed on the silicon nitride layer, for controlling an etch process to selectively remove the tensile silicon nitride layer from the compressive silicon nitride above the P-channel transistor. Thereafter, the stressed etch stop layer may be removed from the N-channel transistor by providing a resist mask and etching the exposed portion of the etch stop layer, using the silicon dioxide stop layer as an etch stop. Next, the tensile silicon nitride layer is deposited, which is subsequently removed from the P-channel transistor on the basis of a corresponding resist mask and the etch indicator layer.
In other approaches, the process sequence for applying and selectively removing the silicon nitride etch stop layers may be reversed, i.e., the tensile silicon nitride may be formed first. In these manufacturing regimes, however, a significant defect rate and contact failures may be observed.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.